DRIVER UPDATE: ADAPTEC MEMORY CONTROLLER / XOR ENGINE


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Adaptec Memory Controller / XOR Engine Driver

Adaptec, Inc. (Milpitas, CA) A exclusive OR(XOR) accumulator engine of a memory controller, the XOR accumulator engine having an XOR. here you can download driver for Adaptec Memory Controller / XOR Engine. DDR memory, they stand for improved performance within SATA II ports, depending on the controller type Integrated XOR engine for optimized parity.


ADAPTEC MEMORY CONTROLLER / XOR ENGINE DRIVERS FOR PC

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Adaptec Memory Controller / XOR Engine Driver

ADAPTEC MEMORY CONTROLLER / XOR ENGINE DRIVER DOWNLOAD

What is claimed is: An exclusive OR XOR accumulator engine for efficiently generating parity from a group of data blocks stored in memory of a data processing system, the XOR accumulator engine comprising: The XOR accumulator engine of claim 1 wherein Adaptec Memory Controller / XOR Engine XOR Adaptec Memory Controller / XOR Engine circuit has a plurality of inputs coupled to a plurality of data sources and wherein the multi-stage shift register has an input coupled to an output of the XOR logic circuit.

The XOR accumulator engine of claim 2 wherein one of the plurality of data sources is an output of the multi-stage shift register coupled to one of the plurality of inputs of the XOR logic circuit, and wherein another of the plurality of data sources is the memory for providing the data blocks to another of the plurality of inputs of the XOR logic circuit.

The XOR accumulator engine of claim 1 wherein the register comprises a bypass circuit configured to create first and second stages of the multi-stage register, whereby to permit the register to accommodate the different sizes of the data blocks. The XOR accumulator engine of claim 4 wherein the bypass circuit comprises a tap multiplexer having a Adaptec Memory Controller / XOR Engine input that couples to an output of the first stage, a second input that bypasses the first stage by intercepting data provided at an input of the multi-stage register and an output connected to an input of the second stage.

The XOR accumulator engine of claim 5 further comprising a control state machine for generating control signals used to control operations within the engine.

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The XOR accumulator engine of claim 6 wherein a first control signal generated by the state machine configures the tap multiplexer to select Adaptec Memory Controller / XOR Engine of its first and second inputs to dynamically adjust the depth of the register to conform with a size of a data block loaded into the input of the multi-stage register. The XOR accumulator engine of claim 7 wherein the multi-stage shift register comprises a plurality of cascaded storage elements interrupted by the tap multiplexer.

The XOR accumulator engine of claim 8 wherein each storage element comprises a set of flip-flops coupled to associated segment multiplexers. The XOR accumulator engine of claim 9 wherein the set of flip-flops are configured as a register segment.

The XOR accumulator engine of claim 10 wherein the memory comprises a bi-directional memory interface having an input data path and an output data path coupled to a plurality of inputs of the XOR logic circuit. The XOR accumulator engine of claim 11 wherein each of the input and output data paths comprises a driver coupled to a latch. The XOR accumulator engine of claim 12 wherein the latch is a D-type flip-flop and the driver is a tri-state buffer circuit, and wherein the tri-state buffer circuit is enabled Adaptec Memory Controller / XOR Engine a second control signal generated by the control state machine.

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The exclusive XOR accumulator engine of claim 14 wherein the multi-stage shift register comprises a plurality of cascaded storage elements. The exclusive XOR accumulator engine of claim 15 wherein the bypass circuit is a tap multiplexer configured and arranged to interrupt the plurality of cascaded storage elements.

The data to be protected are typically divided Adaptec Memory Controller / XOR Engine chunks or blocks of data that are further organized into data groups, each of which consists of a fixed number of data blocks. For a data processing system having a plurality of data storage devices, e. In the context of a RAID implementation, parity protection denotes a type of checksum that allows regeneration of unreadable data in a block by evaluating a function of the data values stored in positionally corresponding data blocks that are not in error.

ADAPTEC MEMORY CONTROLLER / XOR ENGINE WINDOWS 8 DRIVER DOWNLOAD

A memory controller of the data processing system generally performs such an evaluation, typically in connection with a Booleon exclusive OR XOR function. The XOR function is applied bit-by-bit to positionally corresponding bits in each data block of a group and the result is stored in a positionally corresponding bit of a parity block.

ADAPTEC, INC. Adaptec Memory Controller / XOR Engine drivers for Windows XP x86

The parity block for each data grop is then stored on one of the disks containing the data group that the parity block protects. The system comprises a main memory coupled to a memory controller via a memory bus The main memory includes storage locations for holding data blocks B1-B4 of a Adaptec Memory Controller / XOR Engine group transferred from a plurality of disks not shown and the controller contains Adaptec Memory Controller / XOR Engine XOR function for performing parity operations on the data blocks.

The results of the parity operations are then stored in a location in memory The memory controller typically calculates parity for the data blocks by way of a series of read and write operations over the memory bus For example, B1 is acquired from memory via a read access R1 over the busB2 is acquired via a read access R2 over the bus, parity is calculated from these blocks and the partial result is stored in buffer via a write access Wp over the bus.

Likewise, data block B3 is acquired via a read bus access R3the parital parity result is retrieved via a read bus access Rpparity is calculated from these blocks and the partial result is stored via a write bus access Wp.

Finally, B4 is acquired via a read bus access R4the parital parity result is retrieved via a read bus access Rpparity is calculated from these blocks and the total parity result is stored via a write access Wt over the bus. Table 1 summarizes these bus operations required to calculate parity for the data blocks B1-B4. Parity calculations requiring read and write bus accesses by the memory controller to main memory are time consuming and, thus, inefficient.

It is therefore desirable to reduce the number of memory bus accesses required for a memory controller to calculate parity for data blocks stored in a memory of a data processing system.

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